As a switch circuit which uses a MOS-FET, a circuit shown in FIG. 10 or 11 is known. In particular, in the circuit of FIG. 10, when a gate voltage VG of an N-channel MOS-FET (QSW) is approximately 4 to 5 V, the source-drain path of the MOS-FET (QSW) becomes on, but when the gate voltage VG is 0, the source-drain path becomes off.
Meanwhile, also the circuit of FIG. 11 is similar, and when VG=approximately 6 V, the source-drain path of the MOS-FET (QSW) becomes on, but when VG=0, the source-drain path of the MOS-FET (QSW) becomes off. Accordingly, each of those circuits operates as a switch circuit which is controlled with the gate voltage VG.    Patent Document 1: Japanese Patent Laid-Open No. Hei 8-223020    Patent Document 2: Japanese Patent Laid-Open No. 2002-314388